Andes − Powerful System-on-a-Chip for Imaging Radar

Based on the 22 nm CMOS process technology, the Andes SoC (see image) integrates an RF module with a continuous sweep range from 76 GHz to 81 GHz, a typical maximum output power of 14 dBm, and a phase noise of -95 dBc/Hz (@ 1 MHz). It also has a 7-bit phase shifter and high-performance ADC based on a transmission line, allowing flexible waveform generation and various functions like precise digital compensation. Boasting the unique architecture of a quad-core CPU with a digital signal processor (DSP) and a dedicated Radar Signal Processor (RSP), an Andes SoC can offer more than 2500 DMIPS computing power and exceptional signal processing performance.

Owing to the distinctive feature of Andes-Flex-Cascading®, customers can cascade two Andes SoCs through Chip-to-Chip interfaces to readily realize an imaging radar system. This approach not only scales up SoC resources but also simplifies the hardware architecture, optimizes the BOM, and allows software reuse.